View XSA5224CU_8642817.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sa5224 fddi fiber optic postamplifier product specification replaces datasheet ne/sa5224 of 1995 apr 26 ic19 data handbook 1998 oct 07 integrated circuits
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 2 1998 oct 07 853-1594 20141 description the sa5224 is a high-gain limiting amplifier that is designed to process signals from fiber optic preamplifiers. capable of operating at 125mb/s, the chip is fddi compatible and has input signal level-detection with a user-adjustable threshold. the data and level-detect outputs are differential for optimum noise margin and ease of use. also available is the sa5225 which is an ecl 10k version of the sa5224. features ? wideband operation: 1.0khz to 120mhz typical ? applicable in 155mb/s oc3/sonet receivers ? operation with single +5v or 5.2v supply ? differential 100k ecl outputs ? programmable input signal level-detection ? fully differential for excellent psrr to 1ghz pin description d package cazn cazp gnd a d in d out d out v ref v set 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 d in cf jam v cca v cce gnd e st st sd00374 figure 1. pin configuration applications ? fddi ? data communication in noisy industrial environments ? lans ordering information description temperature range order code dwg # 16-pin plastic small outline (so) package 40 to +85 c sa5224d sot109-1 block diagram (6) (2) (1) (16) (13) (12) (8) (9) (10) (11) (7) (3) (16) (15) (5) (4) limiting amplifier ecl buffer jam buffer sd buffer level detector reference d in d in v ref v set gnd a c f gnd e d out d out jam st v cce c azn c azp v cca st sd00375 figure 2. block diagram
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 3 pin descriptions pin no. name function 1 c azn auto-zero capacitor pin. connecting a capacitor between this pin and c azp will cancel the offset voltage of the limiting amplifier. 2 c azp auto-zero capacitor pin. connecting a capacitor between this pin and c azn will cancel the offset voltage of the limiting amplifier. 3 gnd a analog gnd pin. connect to ground for +5v upshifted ecl operation. connect to 5.2v for standard ecl operation. must be at same potential as gnd e (pin 11). 4 d in differential input. dc bias level is set internally at approximately 2.9v. complimentary to d in (pin 5). 5 d in differential input. dc bias level is set internally at approximately 2.9v. complimentary to d in (pin 4). 6 v cca analog power supply pin. connect to a +5v supply for upshifted ecl operation. connect to ground for standard ecl operation. must be at same potential as v cce (pin 14). 7 c f filter capacitor for level detector. capacitor should be connected between this pin and v cca . 8 jam this ecl-compatible input controls the output buffers d out and d out (pins 12 and 13). when an ecl low signal is applied, the outputs will follow the input signal. when an ecl high signal is applied, the d out and d out pins will latch into low and high states, respectively. when left unconnected, this pin is actively pulled-low (jam off). 9 st input signal level-detect status . this ecl output is high when the input signal is below the user programmable threshold level. 10 st ecl compliment of st (pin 9). 11 gnd e digital gnd pin. connect to ground for +5v upshifted ecl operation. connect to a negative supply for normal ecl operation. must be at the same potential as gnd a (pin 3). 12 d out ecl-compatible output. nominal level is v cce 1.3v. when jam is high, this pin will be forced into an ecl high condition. complimentary to d out (pin 13). 13 d out ecl-compatible output. nominal level is v cce 1.3v. when jam is high, this pin will be forced into an ecl low condition. complimentary to d out (pin 12). 14 v cce digital power supply pin. connect to a +5v supply for upshifted ecl operation. connect to ground during normal ecl operation. must be at the same potential as v cca (pin 6). 15 v ref reference voltage for threshold level voltage divider. nominal value is approximately 2.64v. 16 v set input threshold level setting circuit. this input can come from a voltage divider between v ref and gnd a . absolute maximum ratings symbol parameter rating units v cc power supply (v cc - gnd) 6 v t a operating ambient 45 to +85 c t j operating junction 55 to +150 c t stg storage 65 to +150 c p d power dissipation, t a = 25 c (still air) 1 16-pin plastic so 1100 mw note: 1. maximum dissipation is determined by the ambient temperature and the thermal resistance, q ja : 16-pin so: q ja = 110 c/w recommended operating conditions symbol parameter rating units v cc supply voltage 4.5 to 5.5 v t a ambient temperature ranges 40 to +85 c t j junction temperature ranges 40 to +110 c
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 4 dc electrical characteristics min and max limits apply over operating temperature at v cc = 5v 10%, unless otherwise specified. typical data apply at t a = 25 c and v cc = +5v. symbol parameter test conditions sa5224 unit symbol parameter test conditions min typ max unit v in input signal voltage single-ended differential .002 .004 1.5 3.0 v p-p v os input offset voltage 2 50 m v v n input rms noise 2 60 m v v th input level-detect programmability single-ended v in = 200khz square wave 2 12 mv p-p v hys level-detect hysteresis 4 5 6 db i cc v cca + v cce supply current no ecl loading 27 35 ma i inl jam input current pin 8 = 0v 10 10 m a v ohmax maximum logic high 1 0.880 v dc v ohmin minimum logic high 1 1.055 v dc v olmax maximum logic low 1 1.620 v dc v olmin minimum logic low 1 1.870 v dc v ih minimum input for jam = high 1 1.165 v dc v il maximum input for jam = low 1 1.490 v dc notes: 1. these ecl specifications are referenced to the v cce rail and apply for t a = 0 c to 85 c. 2. guaranteed by design. ac electrical characteristics typical data apply at t a = 25 c and v cc = +5v. min and max limits apply for 4.5 v cc 5.5v. symbol parameter test conditions min typ max unit bw 1 lower 3db bandwidth c az = 0.1 m f 0.5 1.0 1.5 khz bw 2 upper 3db bandwidth 90 120 150 mhz r in input resistance pin 4 or 5 2.9 4.5 7.6 k w c in input capacitance pin 4 or 5 2.5 pf t r , t f ecl output 3 risetime, falltime r l = 50 w to v cce - 2v 20-80% 1.2 2.2 ns t pwd pulsewidth distortion 0.3 ns p-p r az auto zero output resistance pin 1 or 2 155 250 423 k w r f level-detect filter resistance pin 7 14 24 41 k w t ld level-detect time constant c f = 0 0.5 1.0 2.0 m s notes: 1. both outputs should be terminated identically to minimize differential feedback to the device inputs on a pc board or substra te.
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 5 ne5212 ne5224 clock recovery & retiming sd00376 figure 3. typical fiber optic receiving system input biasing the data input pins (4 and 5) are dc biased at approximately 2.9v by an internal reference generator. the sa5224 can be dc coupled, but the driving source must operate within the allowable 1.4v to 4.4v input signal range (for v cc = 5v). if ac coupling is used to remove any dc compatibility requirement, the coupling capacitors c1 and c2 must be large enough to pass the lowest input frequency of interest. for example, .001 m f coupling capacitors react with the internal 4.5k input bias resistors to yield a lower 3db frequency of 35khz. this then sets a limit on the maximum number of consecutive a1os or a0os that can be sensed accurately at the system data rate. capacitor tolerance and resistor variation (2.9k to 7.6k) must be included for an accurate calculation. auto-zero circuit figure 5 also shows the essential details of the auto-zero circuit. a feedback amplifier (a4) is used to cancel the offset voltage of the forward signal path, so the input to the internal ecl comparator (a6) is at its toggle point in the absence of any input signal. the time constant of the cancelling circuitry is set by an external capacitor (c az ) connected between pins 1 and 2. the formula for the lower 3db frequency is: f 3db 150 2 r az c az where r az is the internal driving impedance which can vary from 155k to 423k over temperature and device fabrication limits. the input coupling time constant must also be considered in determining the lower frequency response of the sa5224. input signal level-detection the sa5224 allows for user programmable input signal level-detection and can automatically disable the switching of its ecl data outputs if the input is below a set threshold. this prevents the outputs from reacting to noise in the absence of a valid input signal, and insures that data will only be transmitted when the input signal-to-noise ratio is sufficient for low bit-error-rate system operation. complimentary ecl flags (st and stb) indicate whether the input signal is above or below the desired threshold level. figure 6 shows a simplified block diagram of the sa5224 level-detect system. the input signal is amplified and rectified before being compared to a programmable reference. a filter is included to prevent noise spikes from triggering the level-detector. this filter has a nominal 1 m s time constant, and additional filtering can be achieved by using an external capacitor (cf) from pin 7 to v cca (the internal driving impedance is nominally 24k). the resultant signal is then compared to a programmable level, v set , which is set by an internal voltage reference (2.64v) and an external resistor divider (r1 and r2). the value of r1 + r2 should be maintained at approximately 5k. hyst (off) (on) v tl v th sd00377 figure 4. the circuit is designed to operate accurately over a differential 2-12mv p-p square-wave input level detect range. this level, v set /100, is the average of v th and v tl . nominal hysteresis of 5db is provided by the complimentary ecl output comparator yielding v tl v set 139 and v th v set 78 . for example, with v set = 1.2v, a 15.4mv p-p square-wave differential input will drive the st pin high, and an input level below 8.6mv p-p will drive the st pin low. since a ajamo function is provided (pin 8) and can force the data outputs to a predetermined state (d out = low, d out = high), the st and jam pins can be connected together to automatically disable signal transmission when the chip senses that the input signal is below the desired threshold. jam (pin 8) low enables the data outputs. st will be in a high ecl state for input signals below threshold. data in c1 c2 a1 + a3 a6 data out a4 d in d inb r in c az r az 250k w r az 250k w d out d outb 4.5k w r in 4.5k w v bias ecl 100k sd00378 figure 5. sa5224 forward gain path including auto-zero
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 6 50x .25x r 1 c f v cca filter r 2 v ref data in 2.64v st level- detect flags + st low-pass ecl 100k sd00379 figure 6. sa5224 input signal level-detect system r 1 c az r 2 c in1 data in data out 3v level-detect status 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 0.1 m f 0.1 m f 0.1 m f 0.1 m f 0.1 m f 5v c in2 0.1 m f r 3 r 4 r 5 50 w 50 w 50 w c azn c azp gnd a d in d in v cca c f jam v set v ref v cce d out d out gnd e st st 5v sd00380 figure 7. application with v cc = 5.0v note: a 50 w resistor is required from pin 9 to 3v only if the st pin is required to meet 100k ecl specifications. die sales disclaimer due to the limitations in testing high frequency and other parameters at the die level, and the fact that die electrical characteristics may shift after packaging, die electrical parameters are not specified and die are not guaranteed to meet electrical characteristics (including temperature range) as noted in this data sheet which is intended only to specify electrical characteristics for a packaged device. all die are 100% functional with various parametrics tested at the wafer level, at room temperature only (25 c), and are guaranteed to be 100% functional as a result of electrical testing to the point of wafer sawing only. although the most modern processes are utilized for wafer sawing and die pick and place into waffle pack carriers, it is impossible to guarantee 100% functionality through this process. there is no post waffle pack testing performed on individual die.
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 7 since philips semiconductors has no control of third party procedures in the handling or packaging of die, philips semiconductors assumes no liability for device functionality or performance of the die or systems on any die sales. although philips semiconductors typically realizes a yield of 85% after assembling die into their respective packages, with care customers should achieve a similar yield. however, for the reasons stated above, philips semiconductors cannot guarantee this or any other yield on any die sales. 1 2 3 4 5 6 7 8910 11 12 13 14 15 16 cazn cazp gnda din din v cca cf jam st st gnd e dout v cce v ref dout v set ecn no.: 01673 1991 feb 8 sd00492 figure 8. sa5224 bonding diagram
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 8 so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 9 notes
philips semiconductors product specification sa5224 fddi fiber optic postamplifier 1998 oct 07 10 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 10-98 document order number: 9397 750 04628
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

▲Up To Search▲

Price & Availability of XSA5224CU

	To Download XSA5224CU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .